Method and apparatus for bus optimization in a PLB system
US6671752B1 · kind B1 · utility
8Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2000 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jan 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus, and a computer program product for optimising a bus in a Processor Local Bus (PLB) system are disclosed. A master engine performs a transfer transaction of N bytes of data on the bus of the PLB system. A type of read or write data transfer to be performed by the master engine is determined to optimize operation of the bus in response to a transfer request received asynchronously from a device coupled to the bus. This involves a request type determination function. Data is asynchronously transferred using a FIFO between the device and the bus dependent upon the determined type of transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.