System and method of saving and restoring registers in a data processing system
US6671762B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1997 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Dec 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task “as is” upon the occurrence of a task switch to MMX, or another context. The address of the area where the FPU state is saved is maintained in a save area address register. The secondary register is then utilized by the other context to store intermediate results of executed instructions. In the majority of cases when a context switch back to floating point operations occurs, the previous state is restored from the primary register without incurring the latency of retrieving the instructions and data from the memory subsystem. In addition to the secondary register, a snooping mechanism will use the address of the state save area to determine if the state save area was modified. If the state save area is modified, then the floatin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.