Hash CAM having a reduced width comparison circuitry and its application
US6671771B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jan 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hash CAM is provided with a first and a second memory array, and comparison circuitry. The first memory array is used to store an m-bit input in a partitioned manner suitable for being subsequently output in a successive manner in portions of size m/p, where m and p are positive integers, with m being greater than or equal to p. The second memory array is used to store a plurality of threaded lists of entries, with each entry having a comparand also m-bit in size and stored in the same partitioned manner suitable for being selectively output in the same successive manner in portions of size m/p. The successive output is made responsive to an n-bit index generated in accordance with the m-bit input, with n being also a positive integer, but smaller than m. The comparison circuitry, which is complementarily reduced in width, is used to successively compare corresponding portions of the m-bit input and the selectively output comparand(s) to cumulatively determine if the m-bit input relates to one of the output comparands in a predetermined manner. In each of a number of applications, a look-up engine is provided with the hash CAM. In one particular application, a forwarding section …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.