Method and apparatus for testing memory
US6671836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing DRAM is described. The method and apparatus causes the DRAM pins to be reconfigured to provide a direct path between the memory core and the DRAM pins. This reconfiguration allows the memory core to be “seen” without probing and also allows faster and simpler testing with a more traditional protocol. The method and apparatus for testing also provides for several options to further increase testing speed. These options include an internal block compare and a core noise option. The internal block compare performs an internal parallel bit by bit comparison of read data to the contents of a write buffer and generates an error signal if a mismatch occurs. The core noise option simulates the noise that can occur during the normal mode of operation that does not occur during testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.