Method of designing hierarchical layout of semiconductor integrated circuit, and computer product
US6671858B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2001 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In designing an integrated circuit, low-order blocks are arranged in a formation area of a high-order block in a core area with small spacing. Arrangement of and wiring between cells are performed in the low-order blocks. Input/output terminals used for connection between the cells also serve as signal connection terminals of the low-order blocks. Connection between the low-order blocks is performed by connecting the input/output terminals to each other with signal connection wiring. The signal connection wiring is constituted by a wiring layer and a via through a high-order block. The wiring layer and via constituting the signal connection wiring are different from the wiring layer and via used for connection between cells in low-order blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.