Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US6673667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2001 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Aug 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.