Method for manufacturing a semiconductor device having hemispherical grains
US6673673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.