Active matrix substrate and manufacturing method therefor
US6674093B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Jan 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another from layer to layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer (102 of FIG. 6) and a TFF area. A drain electrode layer (106 of FIG. 6) is formed by a first passivation film (105 of FIG. 6) via a first passivation film (105 of FIG. 6) formed as an upper layer. In a second passivation film (107 of FIG. 6) formed above it are bored an opening through the first and second passivation films and an opening through the second passivation film. A wiring connection layer is formed by ITO (108 of FIG. 6) provided as an uppermost layer. A storage capacitance unit, comprised of the first and second passivation films sandwiched between the gate electrode and an electrode layer formed as a co-layer with respect to the gate electrode, is provided in the pixel electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.