Recording clock generation circuit
US6674330B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Aug 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.