Robust clock circuit architecture
US6674332B1 · kind B1 · utility
48Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Sep 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/235
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.