Multi-instruction stream processor
US6674536B2 · kind B2 · utility
43Cited by
148References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1998 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Feb 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses apparatus for, and a method of, rendering image data prior to outputting of the resulting image. A graphics co-processor (224) is utilized together with a host CPU (202), the former having a plurality of data calculation streams (241, 242, 243) arranged in parallel fashion. Only one of the data calculation streams (241, 242, 243) is operated at any one time. Preferably at least one (242) of the data calculation streams is able to be reconfigured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.