Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture
US6674676B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2003 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | May 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.