Sense amplifier control circuit of semiconductor memory device
US6674678B2 · kind B2 · utility
8Cited by
7References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Oct 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier section of a semiconductor memory device includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of layout units respectively including circuit portions of sense amplifiers, wherein the layout units are disposed in the array of layout units at intervals smaller than intervals of the bit line pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.