Fast DRAM control method and adapted controller
US6675256B1 · kind B1 · utility
12Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 17, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Nov 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a memory controller for controlling a DRAM including a memory plane formed with an array of memory cells and at least two cache registers. An access request including a page address, a column address, a write or read order, a possibly data to be written is received. The page address of the current request is compared with the page address of the preceding request and, if they are different, the controller stores the current request page in one non-used of the cache registers, preferably that which has not been used last.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.