Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested
US6675273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Nov 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuitry is designed to efficiently obtain a predictable array output when an invalid address is requested. The memory circuit comprises an invalid word line path in addition to the standard valid word line path. In order to provide correct output, a dummy word line output of a first decode logic is delayed and the delayed dummy word line output is ANDed with a word line output to update the data out latch. Further, the invalid word line output of a second decode logic is also delayed, and the delayed invalid word line output is ORed with the delayed dummy word line output to reset the control logic. ORing the delayed signals allows the predictable output to be provided at a same clock time, irrespective of whether a valid address or an invalid address is decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.