Integrated circuit with multiple processing cores
US6675284B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1999 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Aug 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received. The adaptor further includes receive circuitry having circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits, circuitry for converting the bit sequence into parallel data and control signals for the on-chip functional circuitry and circuitry for transmitting parallel data and control signals on the communication channel identified by said channel identification bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.