Method and apparatus for phase-lock in a field programmable gate array (FPGA)
US6675306B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.