Majority vote circuit for test mode clock multiplication
US6675312B1 · kind B1 · utility
1Cited by
6References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Jan 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.