Rendezvous of processors with OS coordination
US6675324B2 · kind B2 · utility
27Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1999 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Sep 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.