Distributed test architecture for multiport RAMs or other circuitry
US6675336B1 · kind B1 · utility
8Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Nov 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.