Built-in self verification circuit for system chip design
US6675337B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Oct 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit. The bi-directional signal flow switch and the first unidirectional signal flow switch are used for controlling the input terminal of the built-in verification circuit and the signal flow direction of the test pattern generator. The second and the third unidirectional signal flow switch are used for controlling the signal…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.