Patent · US Expired

System of management of the trimming of integrated fuses within a scan test architecture

US6675360B1 · kind B1 · utility

23Cited by

7References

48Claims

0Family size

Assignee

STMicroelectronics SA

Inventors

Giuseppe Cantone · Bareggio, IT
Roberto Cappelletti · Cornaredo, IT

Key dates

Filing date	Nov 21, 2000
Grant date	Jan 6, 2004
Priority date	—
Expiry date	Feb 5, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C17/16
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Functions for simulating, burning and controlling integrated fuses of a device are provided by a dedicated circuit which, instead of differing from other circuits, is integrated by sharing part of the registers with the circuit that normally exists to scan test the integrity of the state of the device. The architecture is simplified and only requires an additional pin as compared to a common scan test circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.