Method of selectively forming silicide
US6677234B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1999 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Aug 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76889
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a crystalline silicon body a shallow trench insulation is made by etching a groove and filling it with silicon oxide. Ridges of polysilicon are made on the surface of the silicon body by applying a layer of polysilicon and patterning it with a known technique. Spacers of silicon nitride are provided on the side walls of the polysilicon ridges. A first layer of silicon nitride, a second layer of TEOS and a patterned resist layer are applied. The TEOS layer is etched by immersion in a solution of 0.36% HF for 14 minutes. Subsequently, the resist is stripped in H2SO4 or peroxide. The silicon nitride layer is etched by immersion in phosphoric acid of 165° C. for 15 minutes using the TEOS layer as a mask. A titanium layer is applied. Subsequently, the body is rapidly heated to a temperature of 760° C. at which it is kept for 20 seconds. During this rapid thermal treatment titanium silicide is formed at locations where the titanium is in contact with silicon i.e. on top of the polysilicon ridges and also on the exposed crystalline regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.