Housing for semiconductor chips
US6678163B1 · kind B1 · utility
10Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A housing arrangement for a plurality of semiconductor chips (1) is disclosed, in which each of the chips is received in a respective frame or cassette (4), there being a first electrically conductive member (5), having portions (6) which are in electrical connection with one face of each of the chips and a second electrically conductive member (7), having portions (8) which are in electrical connection with an opposite face of each of the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.