Semiconductor memory device with high-speed operation and methods of using and designing thereof
US6678204B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 27, 2001 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Jan 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.