Hierarchical transmission digital demodulator
US6678336B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2000 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Aug 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0095
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.