DSP with distributed RAM structure
US6678801B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system includes a global bus (14) having associated therewith a global address space with a plurality of processor nodes (10) associated therewith. Each of the processor nodes (10) has a CPU (20) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. A dual port SRAM (DPSRAM)(34) is provided for interfacing between the global bus (14) and the local bus (30). Each DPSRAM (34) for each processor core (10) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node (10), it is only necessary to address the designated DPSRAM (34) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU (20) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM (34). This results in only a single access cycle for transfer of the block of data from the global resources to the designated CPU (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.