Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end
US6678815B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2000 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Dec 7, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for reducing power consumption in a processor front end are provided. The processor includes an instruction cache, a TLB, and a branch predictor. For sequential code execution, the instruction cache is disabled unless the next instruction fetch will cross a cache line boundary, thus reducing unnecessary accesses to the instruction cache. The TLB is disabled unless the next instruction fetch will cross a page boundary, thus reducing unnecessary TLB look-ups. For code branching, the branch predictor is configured to include, for each target address, an indication of whether the target address is in the same page as the corresponding branch address. When a branch occurs so as to cause access to a given entry in the branch predictor, the TLB is disabled if the target address is in the same page as the branch address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.