Processor control flow monitoring using a signature table for soft error detection
US6678837B1 · kind B1 · utility
20Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Jan 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for providing integrity of processor control codes in a processing unit are described. In one embodiment, a processing unit contains three circuits where the first circuit further includes an instruction buffer. The second circuit is coupled to the first circuit and contains at least one execution unit. The third circuit is coupled to the first circuit and contains a memory, wherein the third circuit stores error detection code for detecting errors in processor control codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.