Detection apparatus
US6678862B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4169
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A partial response maximum likelihood (PRML) bit detection apparatus is disclosed for deriving a bit sequence (xk) from an input information signal. The apparatus comprises input means for receiving the input information signal. The apparatus further comprises sampling means for sampling the input information signal at sampling instants so as to obtain samples (zk) of the information signal at said sampling instants. The apparatus also comprises calculating means (50, 70) for (a) calculating (50) at a sampling instant ti for one or more of a plurality of states sj (Sa, Sb, Sc) at said sampling instant, an optimum path metric value PM(sj,ti) and for determining for said one or more states a best predecessor state at the directly preceding sampling instant ti−1, a state at said sampling instant identifying a sequence of n subsequent bits. The apparatus further comprises calculating means for (b) establishing (70) the best path from the state at the said sampling instant ti having the lowest optimum path metric value, back in time towards the sampling instant ti−N via best predecessor states, established earlier for earlier sampling instants, to establish an optimum state …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.