Method for connecting electronic components to a substrate, and a method for checking such a connection
US6678948B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2000 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Dec 11, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for connecting an electronic components to a carrier substrate is described. At least one pad of the component is connected electrically conductively to at least one pad on an upper surface of the carrier substrate. A solder bump is deposited on at least one of the pads to be connected, the component is alignedly mated with the carrier substrate, and the at least one solder bump is soldered in order to wet the contact surfaces.It is provided that during the soldering, the at least one solder bump is deformed within the contacting plane in such a way as to achieve a degree of deformation that permits the two-dimensional analysis of said degree of deformation by a radiograph of the interconnection site.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.