ESD protective transistor
US6680493B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 20, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Oct 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
An ESD protective transistor comprises a heavily doped p-type base region which is arranged in a lightly doped p-well and which is provided with a first terminal. Furthermore, a heavily doped n-type emitter region is arranged in the lightly doped p-well. A heavily doped n-type collector region is separated from the lightly doped p-well through a lightly doped n-type region and is provided with a second terminal. The heavily doped n-type emitter region is not short-circuited with the heavily doped base region viy a common electrode and is of floating design. The doping types of the respective regions may be reversed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.