Symmetrical CML logic gate system
US6680625B1 · kind B1 · utility
4Cited by
3References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 31, 2002 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1738
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number (14) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number (10) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.