Phase splitter circuit with clock duty/skew correction function
US6680637B2 · kind B2 · utility
30Cited by
8References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2002 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Sep 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase splitter circuit includes a first signal transfer path for receiving an input signal to output a first output signal, a second signal transfer path for receiving the input signal to output a second output signal having an inverted phase of the first output signal, and a duty cycle correction circuit for controlling pull-up and pull-down speeds of the first and second signal transfer paths to the opposite direction in response to the first and second output signals. According to this structure, duty cycles of the first and second output signals approach 50% and a skew or delay time therebetween approaches “0.”
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.