Method and apparatus for efficient video scaling
US6681059B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1999 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Jul 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T3/40
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital image processor is provided. The digital image processor includes a shift register having a number of serially connected registers. The shift register is receptive to an image data word signal and has a plurality of taps. A coefficient store provides a number of quantized coefficients in which the number of coefficients stored corresponds to an integer multiple of the taps. A number of multipliers are provided, each having a first input coupled to a tap of the shift register and having a second input coupled to the coefficient store to receive a coefficient to provide a number of multiplied output. An adder is coupled to the multiplied outputs, wherein the adder generates a filtered and scaled image data output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.