On-chip image reject filter
US6681103B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/1213
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
With the rising popularity in wireless personal communication systems (PCS), there is a need for low-power, low-cost radio receivers. Low cost can be achieved by integrating the required functions as much as possible, thus minimizing the number of off-chip components. The present invention discloses a novel topology for integrating an image reject filter with a traditional low-noise amplifier (LNA) for use in the front-end of a superheterodyne receiver. Previous topologies employing additional filter stages after the LNA have suffered from poor performance and excessive current consumption. Advantageously, the topology of the present invention requires minimal additional circuitry to perform the filtering function, uses only minimal additional current and does not suffer from the same performance limitations as previous topologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.