FIFO memory device suitable for data transfer apparatuses with different data bus widths and method for controlling the same
US6681314B1 · kind B1 · utility
7Cited by
6References
4Claims
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Key dates
| Filing date | Sep 1, 1999 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Sep 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.