Network of parallel processors to faults-tolerant towards said processors and reconfiguration method applicable to such a network
US6681316B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Apr 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.