Dual access instruction and compound memory access instruction with compatible address fields
US6681319B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. A compound address field of the predetermined compound instruction can be arranged at the same bit positions as the address field for a hard compound memory instruction, that is a compound instruction which is programmed. In this case the decoding of the addresses can be started before the operation code …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.