Efficient implementation of error correction code scheme
US6681340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.