Fault detection method for electronic circuit
US6681360B1 · kind B1 · utility
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6References
29Claims
0Family size
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Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318502
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and device for detecting faults in an electronic circuit, such as a multiplexed latch includes n control inputs, p data inputs, and at least one output. The method involves trying to cause the electronic circuit to function to modify the state of the output with respect to a start state, knowing that if the state of the output effectively changes while the control inputs are inhibited, this means that at least one control input is stuck at logic 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.