Cyclic redundancy check for partitioned frames
US6681364B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0072
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An improved method and system for generating a frame check sequence. A multiple-bit data string, M, is received in which M is of the form:anbncndnan−1bn−1cn−1dn−1 . . . a2b2c2d2a1b1c1d1.M is thereafter parsed into multiple subframes of the form:anan−1an−2 . . . a2a1;bnbn−1bn−2 . . . b2b1;cncn−1cn−2 . . . c2c1;anddndn−1dn−2 . . . d2d1.The subframes are padded with zeros resulting in subframes of the form:an000an−1000an−2000 . . . a2000a1000;0bn000bn−1000bn−200 . . . 0b2000b100;00cn000cn−1000cn−20 . . . 00c2000c100;and000dn000dn−1000dn−2 . . . 000d2000d1.A partial check sum is then generated for each of the multiple subframes. Finally, each of the partial check sums are added together such that a frame check sequence for M is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.