Hit-or-jump method and system for embedded testing
US6681374B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2000 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Feb 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This invention presents a new “Hit-or-Jump” system and method for embedded testing of components of communication systems that can be modeled by communicating extended finite state machines. It constructs test sequences efficiently with a high fault coverage. It does not have state space explosion, as is often encountered in exhaustive search, and it quickly covers the system components under test without being “trapped”, as is experienced by random walks. The algorithm has been implemented and applied to embedded testing of telephone services in an IN architecture, including the Basic Call Service (ECS) as well as other supplementary services.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.