Multi-layer RF printed circuit architecture with low-inductance interconnection and low thermal resistance for wide-lead power devices
US6681483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2002 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Apr 18, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.