Semiconductor device having multilevel interconnections and method of manufacture thereof
US6682999B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1999 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Oct 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides, in one aspect, a method for fabricating an interconnect system within a semiconductor device. In this particular embodiment, the method comprises forming a conductive layer over a substrate of the semiconductor device, such as a dielectric material, forming a photoresist layer over the conductive layer and patterning the photoresist, forming a selected portion and an unselected portion of the conductive layer, altering the selected portion such that the selected portion has an etch rate different from an etch rate of the unselected portion, and forming an interconnect on the selected or unselected portion. As used herein, the selected portion is defined as that portion of the conductive layer, such as a blanket seed layer, that is subject to the alteration process as discussed herein. The selected portion may be, depending on the embodiment, within a footprint of the interconnect or outside the footprint of the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.