Reduced architecture for multibranch feedforward power amplifier linearizers
US6683495B2 · kind B2 · utility
17Cited by
26References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier linearizer circuit has a signal cancellation circuit including a signal adjuster having M branch signals (M≧1), and a distortion cancellation circuit including a signal adjuster having N branch signals (N≧1). The linearizer has a controller for adaptively controlling the M-branch and N-branch signal adjusters. The controller has only one monitor receiver to monitor the M branch signals and only one monitor receiver to monitor the N branch signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.