Direct memory swapping between NAND flash and SRAM with error correction coding
US6683817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2002 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | May 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.