System for checking data integrity in a high speed packet switching network node
US6683854B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1999 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Mar 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for checking the integrity of data transfer in a switching element in a high speed packet switching network node where multicasting is performed by simultaneously shifting data from a first shift register into the targeted device shift registers. The outputs of the device registers are fed back into the first shift register. The checking system includes a device select circuit for selecting the targeted via a set of select lines and a negative OR gate circuit. The select line signals and the first register output are inputs to the OR gate, the output of which is fed back to the first register. A comparator circuit has inputs supplied by the device select lines and the outputs of the device registers. A processor compares the contents of the first register to the outputs from the logic comparator circuit to test whether the data has been properly multicast to the targeted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.