Single-event upset immune frequency divider circuit
US6683932B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2002 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Jul 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.