Method and predictor for streamlining execution of convert-to-integer operations
US6684232B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.